The present invention is directed, in general, to semiconductor devices with bipolar transistors and associated methods of manufacture and, more specifically, to a bipolar transistor having a low dielectric constant (K) material in the emitter region and a method of manufacture therefore.
The advent of the integrated circuit has had a significant impact on various types of communication devices. The integrated circuit has been incorporated into both radio frequency applications and high speed communication network systems. While operation speeds of these communication devices have dramatically increased, the demand for yet faster communication devices continues to rise. Thus, the semiconductor manufacturing industry continually strives to increase the overall speed of the integrated circuit. One way in which the semiconductor industry has increased the speed of the integrated circuit is to continue to shrink the size of the transistor. Over the last few years, the device size of the transistor has gone from 0.5 xcexcm to 0.32 xcexcm to 0.25 xcexcm and now transistor device sizes are heading to the 0.12 xcexcm range and below. As transistor device sizes have continued to dramatically decrease, with each decrease in size the semiconductor industry has faced new challenges.
One such challenge is elimination of parasitic capacitance. This is particularly important for communication devices and communication network systems in general. One integrated circuit component that is often incorporated into these communication devices and networks, is the bipolar transistor. The bipolar transistor facilitates the faster operating speeds that are needed for complex communication network systems. However, as device sizes have continued to shrink into the sub-micron size, the bipolar transistor has also been a source of decreased operating speed due to the increased parasitic capacitance. For example, in some cases, emitter-base parasitic capacitance (CEBP) can be as high as 60% of the total emitter-base capacitance (CEB), which severely slows down emitter coupled logic (ECL) type circuits, which are often used in high-speed communication network systems.
The industry has attempted to solve this problem by producing a smaller emitter-base overlap to reduce CEBP. However, the production of this device often requires more advanced and expensive photolithographic tools. Moreover, there are increased possibilities of device parameter variations that can cause uniformity and yield issues during production. In addition, non-ideal emitter-base recombination current can severely degrade device performance.
Accordingly, what is needed in the art is a bipolar transistor and a method of manufacture therefore, that avoids the disadvantages associated with the prior art bipolar transistors.
To address the above-discussed deficiencies of the prior art, the present invention provides a bipolar transistor located on a semiconductor wafer substrate. In one embodiment, the bipolar transistor comprises a collector located in the semiconductor wafer substrate; a base located in the collector; and an emitter located on the base and in contact with at least a portion of the base, wherein the emitter has a low K layer located therein. In one embodiment, the low K layer is located proximate a side of the emitter. More preferably, however, the low K layer is located proximate opposing sides of the emitter. In all embodiments, however, the low K layer does not interfere with the proper functioning of the bipolar transistor. The low K layer, however, does substantially reduce the emitter-base capacitance typically associated with conventional bipolar transistors.
Thus, in one embodiment, the present invention provides a bipolar transistor that reduces emitter-base parasitic capacitance, and thereby, decreases overall capacitance and allows for faster integrated circuit operating speeds. The bipolar transistor provided by the present invention is also easily incorporated into existing complementary metal oxide semiconductor (CMOS) technology without the need for additional equipment, cost or fabrication time.